SwiftCTS: Machine Learning Framework Accelerates Clock Tree Synthesis in Chip Design
Researchers have developed SwiftCTS, a machine learning framework that dramatically speeds up Clock Tree Synthesis (CTS), a computationally expensive stage in semiconductor physical design. The system uses physics-informed statistical features and gradient-boosted models to make predictions in under a millisecond and evaluate 100,000 design configurations in under ten seconds. This advancement could significantly reduce design iteration time and improve optimization of power consumption, wirelength, and timing metrics in chip manufacturing.
SwiftCTS addresses a critical bottleneck in semiconductor design by replacing expensive iterative simulations with a fast surrogate model. The framework combines lightweight physics-grounded features with gradient-boosted ensembles, enabling CPU-based training in under five seconds and GPU-free inference at sub-millisecond speeds. A key innovation is a K-shot multiplicative calibration mechanism that adapts predictions to new, unseen chip architectures using just one or two reference runs, reducing power prediction error from 24.5% to 3.3% and wirelength error from 56.6% to under 1%. When integrated with an evolutionary optimizer, the system evaluates 100,000 CTS configurations in under ten seconds and generates Pareto-optimal design frontiers. Validation within the OpenROAD open-source design flow confirms prediction errors below 0.5% for power and wirelength metrics, with timing skew predictions accurate to within five picoseconds, consistently outperforming default tool heuristics.
What different sources said
- arXiv cs.LGCenter
SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration
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