RTL-BenchLS: New Large-Scale Benchmark for LLM-Based Hardware Design Automation
Researchers introduced RTL-BenchLS, a large-scale benchmark containing over 10,000 formally verified Verilog designs for evaluating large language models on hardware design tasks. The benchmark addresses limitations of existing benchmarks by covering more complex designs and introducing three novel reasoning and generation tasks beyond traditional specification-to-RTL generation. The work is significant because it reveals that even frontier LLMs achieve only 12-28% performance on these tasks, indicating substantial room for improvement in LLM-based hardware design automation.
RTL-BenchLS is a new benchmark dataset designed to evaluate large language models on register-transfer level (RTL) hardware design and reasoning tasks. The benchmark contains over 10,000 formally verified Verilog designs that are substantially larger and more complex than designs in existing benchmarks. Beyond the traditional specification-to-RTL generation task, the researchers propose three novel evaluation tasks: round-trip reasoning, masked-content reasoning, and repository-issue reasoning. Two of these tasks are self-supervised, which resolves the scaling bottleneck that has limited previous benchmarks—the difficulty of obtaining aligned, high-quality labeled data for real-world designs. All tasks are verified through formal equivalence checking rather than manual testbenches. Evaluation of eight LLMs shows that even the best-performing models achieve only 23% accuracy on natural-language round-trip reasoning, 28% on masked-content reasoning, and 12% on repository-issue fixing, demonstrating that RTL-BenchLS is substantially more challenging than existing benchmarks.
What's missing
The paper does not discuss potential limitations of formal equivalence checking as a verification method for all task types, nor does it address how the benchmark might generalize to hardware design practices outside the Verilog ecosystem or to emerging design methodologies.
What different sources said
- arXiv cs.CLCenter
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
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