Researchers Develop AI Framework to Optimize Chip Design Through Strategic Macro Placement Sequencing
A new machine learning framework called OrderPlace uses large language models to automatically discover optimal sequences for placing macros (large functional blocks) in chip design, rather than relying on static heuristics. The research demonstrates that the order in which macros are placed significantly impacts the final design quality, with early suboptimal decisions constraining the solution space. This work addresses a previously underexplored dimension of chip physical design optimization that could improve efficiency in semiconductor manufacturing.
Researchers have introduced OrderPlace, a proxy-guided LLM evolution framework designed to automatically discover optimal macro placement sequences in chip physical design. Macro placement is a critical step in determining solution quality for high-dimensional combinatorial optimization problems in semiconductor design. While recent machine learning advances have focused on spatial coordinate determination, the temporal dimension of placement sequencing has remained governed by static heuristics such as area- or connectivity-based ordering. The study demonstrates that placement sequence is not merely a preprocessing step but a decisive optimization factor, where suboptimal early decisions create irreversible cascading effects that constrain the solution space. OrderPlace explores a broader space of code-level policies ranging from static scoring metrics to dynamic physics-inspired mechanisms, using a lightweight proxy evaluation mechanism to efficiently filter candidates. Experimental results on standard ISPD 2005 benchmarks show OrderPlace discovers novel ordering strategies that reduce wirelength by 34.04% compared to WireMask-EA and 14.08% compared to state-of-the-art EGPlace methods.
What's missing
The paper's own limitations and scope constraints are not detailed in the abstract, such as whether findings generalize beyond ISPD 2005 benchmarks, computational overhead of the LLM evolution process compared to traditional heuristics, or applicability to different chip design scales and technologies.
What different sources said
- arXiv cs.LGCenter
LLM-Guided Neural Architecture Search for Robust Co-Design of Physical Neural Networks
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