Researchers Develop AI Framework to Optimize Chip Design Through Strategic Macro Placement Sequencing
Researchers have proposed OrderPlace, a framework that uses large language models to automatically discover optimal macro placement sequences in chip physical design. The work argues that the order in which chip macros are placed — not just their spatial coordinates — is a decisive factor in design quality, yet has been largely governed by static heuristics. The approach reduces wirelength by up to 34% compared to existing methods, potentially improving chip performance and design efficiency.
A team of researchers has introduced OrderPlace, a proxy-guided LLM evolution framework targeting the temporal dimension of macro placement in chip physical design — a step that determines how large functional blocks are arranged on a chip. The paper argues that suboptimal early placement decisions create irreversible 'domino effects' that constrain the overall solution space, making sequence order a critical but underexplored variable. Rather than relying on manually crafted heuristics such as area- or connectivity-based ordering, OrderPlace uses LLMs to explore a broader space of code-level placement policies, including both static scoring metrics and dynamic physics-inspired mechanisms. To avoid the prohibitive computational cost of evaluating every candidate sequence with a full placement run, the framework employs a lightweight proxy evaluation mechanism using a deterministic greedy probe to efficiently filter candidates. Tested on the standard ISPD 2005 benchmarks, OrderPlace reduces wirelength by 34.04% relative to WireMask-EA and 14.08% relative to the current state-of-the-art method EGPlace. The paper has been accepted to ICML 2026.
What's missing
The study evaluates performance on the ISPD 2005 benchmark suite, which is over two decades old; it is unclear how well the discovered strategies generalize to modern, larger-scale chip designs or proprietary industrial benchmarks. Runtime and computational cost of the full OrderPlace pipeline (beyond the proxy evaluation) relative to baseline methods are not detailed in the abstract. The paper does not address whether the LLM-generated policies are interpretable or transferable across different chip design tools.
What different sources said
- arXiv cs.LGCenter
LLM-Guided Neural Architecture Search for Robust Co-Design of Physical Neural Networks
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