Operator Fusion Strategy Reduces LLM Inference Latency on Tensix Architecture
Researchers have proposed an operator fusion technique for running large language model inference on Tenstorrent's Tensix hardware, achieving up to 37.44% latency reduction in attention operations. The method fuses RMSNorm with matrix multiplication to keep intermediate data in on-chip SRAM rather than repeatedly accessing slower DRAM, and uses a network-on-chip multicast mechanism to coordinate multi-core parallelism. The work demonstrates that hardware-specific operator scheduling can meaningfully improve on-device LLM efficiency without significant numerical degradation.
A preprint submitted to arXiv presents an operator fusion strategy designed to reduce inference bottlenecks for Transformer-based large language models running on Tenstorrent's Tensix architecture, specifically tested on the Wormhole platform. The core technique fuses RMSNorm normalization with subsequent matrix multiplication operations in both the self-attention and feed-forward network (FFN) components, allowing memory-bound and compute-bound operations to execute back-to-back within on-chip SRAM and thereby reducing costly DRAM reads and writes of intermediate tensors. To extend the approach across multiple cores, the authors leverage a network-on-chip (NoC) multicast mechanism in which designated row and column master nodes distribute inputs and weights across the core mesh, reducing DRAM bandwidth contention. Experiments using Qwen2.5-0.5B, Qwen3-0.6B, and Qwen3-4B models show latency reductions of up to 37.44% for attention blocks and 15.89% for MLP blocks, with up to 7.91% reduction per full decoder layer. Numerical accuracy, measured via Pearson Correlation Coefficient, remained above 98.75% across all tested configurations, indicating the optimizations do not materially compromise output fidelity.
What's missing
The study evaluates only relatively small models (up to 4B parameters) on a single hardware platform (Wormhole); generalizability to larger models, other Tensix generations, or competing accelerator architectures is not established. Throughput (tokens per second) and energy efficiency metrics are not reported alongside latency, limiting a full picture of practical deployment gains. The paper does not compare against alternative fusion strategies or existing compiler-level optimizations on the same hardware.
What different sources said
- arXiv cs.LGCenter
Operator Fusion for LLM Inference on the Tensix Architecture
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