Operator Fusion Strategy Reduces LLM Inference Latency on Tensix Architecture
Researchers propose an operator fusion technique that optimizes large language model inference on Tenstorrent's Tensix hardware by fusing RMSNorm with matrix multiplication operations. The approach leverages on-chip SRAM and a network-on-chip multicast mechanism to reduce memory bandwidth bottlenecks. Experiments demonstrate latency reductions of up to 37.44% for attention operations and 15.89% for MLP layers while maintaining numerical accuracy above 98.75%.
A new study addresses inference efficiency challenges for Transformer models running on Tenstorrent's Tensix architecture through operator fusion—combining RMSNorm with matrix multiplication in both self-attention and feed-forward network layers. By executing memory-bound and compute-bound operations sequentially in on-chip SRAM, the approach significantly reduces intermediate data transfers to and from DRAM while minimizing scheduling overhead. The technique employs a network-on-chip multicast mechanism with row and column master nodes to distribute inputs and weights across the processor core mesh, alleviating DRAM bandwidth contention in multi-core scenarios. Testing on the Wormhole platform using Qwen2.5-0.5B, Qwen3-0.6B, and Qwen3-4B models showed latency improvements of up to 37.44% for attention operations and 15.89% for MLP layers, with per-decoder-layer gains reaching 7.91%, while maintaining a Pearson Correlation Coefficient above 98.75% to confirm numerical consistency.
What's missing
The study does not discuss comparison with alternative optimization techniques (e.g., quantization, pruning, or other fusion strategies) on the same hardware, limiting assessment of relative effectiveness. Additionally, power consumption and thermal implications of the approach are not reported, which are relevant for on-device deployment considerations.
What different sources said
- arXiv cs.LGCenter
Operator Fusion for LLM Inference on the Tensix Architecture
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