AttentionCap: Transformer Model Improves Capacitance Extraction for Advanced Chip Design
Researchers have developed AttentionCap, a transformer-based deep learning model that improves the accuracy and speed of capacitance matrix extraction for semiconductor chip design. The model addresses limitations of existing rule-based and CNN-based methods by working across multiple metal layers and process nodes, achieving significantly lower error rates. This advancement has practical value for electronic design automation (EDA) workflows as semiconductor manufacturing moves to increasingly advanced nodes.
AttentionCap is a specialized transformer architecture designed to learn capacitance matrices—a critical component in chip design extraction. The model incorporates a Gram representation framework, a physics-aligned symmetric-attention output layer, and a normalized Laplacian loss function. It includes process-node embedding to enable learning across multiple manufacturing nodes. When trained on synthetic data and tested on unseen real chip designs in multi-layer, multi-node settings, AttentionCap achieved 0.67% self-capacitance error and 3.99% coupling-capacitance error, substantially outperforming CNN-based baselines with 4.6× and 5.7× lower errors respectively, while running 192× faster. The model also demonstrates strong transferability, accurately adapting to new process nodes with only 5,000 samples and 4,000 fine-tuning steps.
What's missing
The paper does not discuss potential limitations of the synthetic training data or how well the model generalizes to real-world manufacturing variations and edge cases beyond the tested scenarios. Additionally, computational requirements for training and deployment infrastructure are not detailed.
What different sources said
- arXiv cs.LGCenter
AttentionCap: Transformer Based Capacitance Matrix Learning Toward Full-Chip Extraction
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